Example: 4-bit adder (represent integers in the range 7 to +7)
超前进位加法器
Carry look-ahead adder (CLA) also known as a fast adder.
RCA 第 n 号全加器要输出计算结果至少要等到第 n-1 号全加器把进位信息传过来，如果级数很高则会出现组合逻辑延时过长的情况。
超前进位加法器的思想是并行计算进位
The design involves two Boolean functions named Generate and Propagate.
计算的方式如下：
💡
和 由对应的 和 生成
Example: 4-bit Carry Look-Ahead Adder
💡
要展开为只关于输入项 。
若保留 ，相当于又要延迟进位
设计步骤
:
final carry
加减法器
Example: 4-bit adder/subtractor
When S = 0, the circuit is an adder.
When S = 1, the circuit is a subtractor.（负数使用补码 Two's complement ）
多路转换器
信号选择器 / 复用器
A multiplexer (also known as a "mux") is a is a digital circuit that selects one of several input signals and passes the selected input to a single output.
The output can change at any instant in time while the Enable input is set HIGH.
A flip-flop has two inputs and two outputs. The outputs (Q and Q’) are complements of each other.
When Q = 1; Q’ = 0, the flip is said to be in a set state.
When Q = 0; Q’ = 1, it is said to be in a reset state.
SR Latch
SR latch is constructed from two cross- coupled NOR gates
逻辑图(Logic diagram)
功能表(Function table)
状态图 (State diagram)
特征方程(characteristic equation)
（约束条件：S 和 R不能同时取1）
D Latch
One way to eliminate the undesirable undeined state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time
命名来源它可以在内部存储元件中保存数据 (data)
The binary information present at the data input of the latch is transferred to the output when the control input is enabled (1)
When the control input is disabled (0), the binary information that was present at the data input at the time the transition in occurred is retained at the output until the control input is enabled again
触发器
Flip-flop
受时钟控制，只有被触发 (trigger) 时才产生输出。
Clocked version of Latch flip-flop
Flipflops often have additional inputs that allow them to be set and reset independently of the clock input. Such inputs are known as asynchronous inputs.
The inputs that asynchronously set the flipflop are called preset.
The inputs that asynchronously reset the flipflop are called clear.
触发器响应时钟变化的方式
边沿触发式(edge-triggered)
只有在时钟由 0 变为 1 或者由 1 变为 0 那一瞬间触发器才被触发
positive-edge clock
nositive-edge clock
其他所有时间（包括时钟脉冲维持为1)，触发器都处于无效状态
脉冲触发式 (pulse-triggered)
也称为“主从触发”
时钟脉冲 (Clock pulse)
当出现时钟脉冲时， 输入信号控制触发器的状态（准备触发）
当没有出现时钟脉冲时（信号稳定后），触发器的状态才正式发生改变
CP 在下降沿时封锁输入信号，并读取已在 CP 经上升沿后存储进“主存储器”的输入状态。
水平触发式(level-triggered)
只有在时钟信号保持某个逻辑电平时，输入信号的变化才会影响锁存器的输出。
通常用于异步电路中，输入信号的变化必须立即反映在输出信号上。
Explain the main difference between an edge-triggered and a level-triggered flip-flop.
Edge-triggered flip-flops respond only to changes on the rising or falling edge of the clock signal, while level-triggered flip-flops respond to changes whenever the clock signal is at a particular logic level.
JK flip-flop
A combination of the SR and T, in that it behaves like an SR flip flop, except that causes the flip-flop to change states.
Characteristic table
Master-slave JK flip-flop
主从式触发器由主触发器和从触发器组成。
相比普通触发器而言，主从式触发器是分步工作，更加稳定。
When the clock pulse is true, the slave flip flop will be in the isolated state, and the system's state may be affected by the J and K inputs. The slave remains isolated until the CP is 1.When the CP set to 0, the master flip-flop passes the information to the slave flip flop to obtain the output.
Assuming the propagation delay of each flip flop is . When the clock makes a transition from the active level to the inactive level, responds later and responds later... The flip flops don’t change simultaneously.
Note that these incorrect intermediate values may cause problems in larger more complex circuits.
电路设计
时序电路是状态依赖的，故又称状态机 (State Machine, SM)。
有限存储单元构成状态机的状态数是有限的，称为有限状态机 (Finite State Machine, FSM)。
米利型时序电路
Mealy State Machine: Sequential system where output depends on current input and state.
穆尔型时序电路
Moore State Machine: Sequential system where output depends only on current state.
步骤
选择触发器类型
构造状态图和状态表
状态化简
Eliminate Redundant States
两个等价状态都可以合并成一个状态
Definition: Two states are equivalent when the next state and outputs for each input column are the same for both states.
状态分配
State Assignment
确定状态编码的位数。
同步时序电路的状态取决于触发器的状态组合，触发器的个数即状态编码的位数。
对每个状态确定编码，从各状态中取各状态组合可能存在多种不同方案。
确定激励方程和输出方程
Excitation Equations ：关于输入与输出的表达式（激励信号即输入信号）
denotes a transition
denotes a transition
denotes a transition
denotes a transition
denotes an optional transition (i.e. any of the above)
